The present invention relates generally to improving the speed and settling characteristics of high resolution digital to analog converters (DACs), and more particularly to improving the speed and settling characteristics of high resolution DACs of the type including a string DAC stage and an interpolation amplifier sub-DAC stage. The invention also relates to further increasing the resolution of DACs of the type including a string DAC stage and an interpolation amplifier sub-DAC stage.
High-speed DACs using current source array structures need to generate currents of the order of 20 mA (milliamperes) in order to achieve 16-bits of fine resolution. These DACs have precision voltage settling errors due to self-heating caused by large currents forced through resistors or through the feedback resistors of I-to-V (current-to-voltage) converters. Also, changing load conditions will linearly affect the settling voltage values of voltage values for current output DACs (IDACs).
DACs based on voltage division (i.e., string DACs) have the desirable characteristics of monotonicity, output voltage stability, low differential non-linearity (DNL), and low “glitch” voltage magnitudes and durations. However, due to inherent RC time constants, voltage division or string DACs are not very suitable for achieving high speed conversions at high resolution. Also, due to the “random-walk” kind of pattern that is inherently involved in the matching of untrimmed resistors connected in a series combination, the integral linearity (INL) of voltage division DACs is not better than approximately 10 bits. Various schemes have been proposed to improve both the linearity and speed of voltage division DACs. Historically, resistor string DAC architectures have been used in high-speed FLASH DACs because of their simplicity and parallel nature wherein all tap voltages of the DAC are available at all times. A need for reducing the resistor string impedance arose to improve the conversion speed, and various solutions for achieving this were developed.
However, during the last decade voltage division DAC architecture lost its popularity for high speed applications because inexpensive DACs having current cell arrays provide orders of magnitude higher sampling rates and reasonably high resolution. For high precision applications, string resistor voltage division DAC architecture has not gained in popularity because it has been very costly to laser-trim the large number of series resistors. Furthermore, in DACs of the kind including R-2R ladders, the required laser-trimming of the resistors has been more economical because a smaller number of resistors is required. Also, high resolutions up to 24 bits have been achieved using delta-sigma DACs, but at very slow conversion speeds.
As the number of resistors in the resistor string DAC stage is increased (e.g., to 10 or even 12 bits), the difference between the string DAC tap voltages VH and VL for each string resistor is reduced to a value between roughly 1 and 4 millivolts, assuming that a precise reference voltage of about 4 volts is being applied across the resistor string, for a typical 5 volt CMOS manufacturing process. Depending on the VT (threshold voltage) mismatch of the input transistors of the differential amplifier, such a small voltage drop across each string resistor could cause DNL problems because of random variation in the transconductance of each differential input transistor pair. It is believed that a 10-bit resistor string (with 210 resistors) is about the largest that can be used and still have an acceptably low DNL, for the case in which 4 volts is applied across the resistor string.
During the last decade, most applications of voltage division DACs in the 8-12 bit range have been in small, low power, low cost, mass-market DAC applications. A 10-bit resistor string with 2-bits of segmentation has provided a good compromise with respect to the amount of chip area required, making multi-channel, low cost string DACs popular in the market. However, achieving monotonicity with “10-4 segmentation” in 14-bit string DACs has resulted in poor manufacturing yields, so 14-bit segmented string DACs have not become popular using conventional analog summing techniques that could not ensure monotonicity.
To summarize, basic, practical high-speed string DACs have not achieved resolutions higher than approximately 10-bits because of their size and complexity.
More recently, a multi-input interpolation amplifier structure has been utilized. One such amplifier is shown in U.S. Pat. No. 5,396,245 by W. C. Rempfer. “Prior Art” FIG. 1 herein is a copy of FIG. 5 of the '254 patent by Rempfer The described interpolation amplifier includes N differential input transistor pairs with (−) side terminals connected together and (+) side terminals externally used as N distinct inputs. Consecutive tap voltages (VH and VL) on the terminals of a string resistor selected by MSB decoding are coupled to the N separate (+) side inputs of the interpolation amplifier, which produces an output voltage that is an average of the voltages applied to the (+) inputs. This structure does not take into account variation of the input transistor transconductances with respect to changing of the interpolation amplifier inputs and has poor integral linearity (INL) properties for the sub-DAC formed by the interpolation amplifier. An improvement can be achieved without using degeneration resistors by separating the tail currents of the N differential input transistor pairs into N equal segments in the manner disclosed in commonly owned U.S. Pat. No. 6,246,351 “LSB Interpolation Circuit and Method for Segmented D/A Converter” issued Jun. 12, 2001 to Yilmaz. “Prior Art” FIG. 2 herein is a copy of FIG. 2 of the '351 Yilmaz patent. The disclosed structure provides good INL for the interpolation amplifier, although overall linearity of the DAC is still dominated by mismatches in the resistor string.
Reducing the size of each differential input transistor pair in the interpolation amplifier stage is difficult, and causes the integrated circuit layout and input transistor matching also to be difficult. The amount of parasitic capacitance increases unacceptably as the number of bits of the interpolation amplifier exceeds 8. In view of the foregoing considerations, 16-18 bits of resolution can be considered to be a reasonable upper limit for DACs of the type including a conventional string DAC stage followed by an interpolating amplifier sub-DAC stage.
X-Y decoding of an array of string resistors in a string DAC is disclosed in U.S. Pat. No. 5,079,552 issued Jan. 7, 1992 to Pelgrom et al.
The accuracy of a resistor-string-based DAC suffers from random-walk type INL errors. That is, the accuracy randomly changes, causing correspondingly random INL errors. The inaccuracy in this type of DAC is caused by random inaccuracies in the resistor string, and can be calibrated in various ways, for example as described commonly assigned U.S. Pat. No. 6,642,869 entitled “Piece-wise Linear Calibration Method and Circuit to Correct the Transfer Function Errors of D/A Converters” issued May 1, 2002 to T. Kuyel and P. L. Parthasarathy, wherein a memory is used to store the required DC calibration coefficients. The memory can be programmed during production testing, and its contents could be transferred to SRAM or DRAM during circuit power-up. The memory could be addressed so that calibration coefficients for a piece-wise linear approximation are loaded into an arithmetic logic unit to generate the calibration codes. When the calibration coefficients are loaded from the SRAM, it is possible to achieve calibration at speeds exceeding 20MSPS (mega-samples per second) at the present state-of-the-art.
The interpolation amplifier structure of above-mentioned U.S. Pat. No. 6,246,351 by Yilmaz does not require substantial input current for CMOS implementations, and it interpolates almost linearly between the two selected string resistor tap voltages. This has resulted in a new generation of segmented monotonic voltage output string DACs having 16-bits of resolution which provide low power, low cost, small die area, exceptionally good DNL (differential nonlinearity), and stable output voltages, but which also suffer from relatively poor INL and low-speed. At the same time, smaller CMOS geometries have enabled arithmetic logic units (ALUs) and FLASH memory to be economically incorporated in DAC cores utilized in various integrated circuits. This generation of segmented string DACs provides a good combination of power, cost, size and accuracy that may rival traditional laser-trimmed R-2R structures.
Since integrated circuit technology is presently capable of the foregoing 16-bit precision segmented string DACs, it would be desirable to provide further improvements in such DACs that could provide high sampling rates and faster precision output voltage settling characteristics. This would be desirable because presently available 16-bit current steering array structures are capable of very high sampling speeds exceeding 500 MHz, but an inherent problem with DACs having such architectures is the necessity of keeping the maximum output current at a relatively high level (e.g., roughly 20 milliamperes) in order to provide adequately fast resolving of the least significant bits. Self-heating occurs when this amount of output current is forced through resistors to provide a current-to-voltage conversion, and this causes the settling accuracy of the DAC output voltage to be significantly degraded. Such high speed current output DACs usually are not utilized for applications requiring output voltage settling any more accurate than 10 bits (0.1% FSR (full scale range)). However, a substantial number of high-speed control applications, especially in fiber optics, need precision output voltage settling at high sampling speeds.
There is an unmet need for a fast segmented DAC of the type including a string DAC as a first stage followed by interpolation amplifier as a second DAC stage and which achieves very high speed and fast output voltage settling at high resolution.
There also is an unmet need for a fast DAC of the type including a string DAC as a first stage followed by an interpolation amplifier as a second DAC stage, and having 24 bit resolution, high speed operation, and fast output voltage settling.
There also is an unmet need for a string DAC architecture with sub-word interpolation which can provide 24-bits of resolution with 10 microsecond output voltage settling with +−0.01 millivolts of absolute accuracy when driving a load that changes with temperature and time.
There also is an unmet need for a high-resolution, fast settling string DAC architecture with sub-word interpolation which can provide a high analog output voltage range, for example from −5 volts to +5 volts, manufactured using conventional low voltage transistor fabrication processes with minimal or no process modification.